library ieee;

use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;

use work.cpu_utils.all;



entity stack is
	generic (
		Tpd : Time := unit_delay;
		data_size: integer := 32;
		address_size : integer := 10
	);
	port (
		clock : in bit;
		data_in : in bit_vector(data_size-1 downto 0);
		data_out : out bit_vector(data_size-1 downto 0);
		a_bus : in bit_vector(address_size-1 downto 0);
		push, pop : in bit
	);
end stack;

--zasto latchuje?
architecture stack_mem of stack is
	constant low_address : integer := 0;
	constant high_address : integer := 2**address_size-1;
	type memory_array is
		array (integer range low_address to high_address) of bit_vector(data_size-1 downto 0);
	shared variable mem : memory_array;
begin
	process(push, clock, a_bus)
	begin
	if push = '1' then 
		if(clock'event and clock='1')then	
				mem(to_integer(a_bus)) := data_in;
		end if;
	end if;
	end process;
	
	process(pop, clock, a_bus)
	begin
	if pop = '1' then 
		if(clock'event and clock='1')then	
			data_out <= mem(to_integer(a_bus)) after Tpd;
		end if;
	end if;
	end process;

end stack_mem;